VLSI IEEE 2014 PROJECT TITLES

2014 IEEE VLSI PROJECT TITLES  Domain:VLSI	Language
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line	VLSI
Runtime Thermal Management for 3-D	VLSI
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler	VLSI
Image Quality Assessment for Fake Biometric Detection: Application to Iris, Fingerprint, and Face Recognition	VLSI
A Frame-Level Rate Control Scheme Based on Texture and Nontexture Rate Models for High Efficiency Video Coding	VLSI
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme	VLSI
A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS	VLSI
A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits	VLSI
A Low Complexity-High Throughput QC-LDPC Encoder	VLSI
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures	VLSI
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain	VLSI
A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture	VLSI
A Synergetic Use of Bloom Filters for Error Detection and Correction	VLSI
A Unified Framework for Outlier Detection in Trace Data Analysis	VLSI
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories	VLSI
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability	VLSI
Analysis and Characterization of Capacitance Variation Using Capacitance Measurement Array	VLSI
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator	VLSI
Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter	VLSI
Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation	VLSI
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane	VLSI
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Waggin	VLSI
Design Techniques to Improve Blocker Tolerance of Continuous-Time Δ Σ ADCs	VLSI
Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor	VLSI
Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three	VLSI
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects	VLSI
Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers	VLSI
Error Correction Encoding for Tightly Coupled On-Chip Buses	VLSI
Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories	VLSI
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs	VLSI
Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study	VLSI
Fast Radix-10 Multiplication Using Redundant BCD Codes	VLSI
Fast Sign Detection Algorithm for the RNS Moduli Set 2n+1-1, 2n-1, 2n	VLSI
Fat-Tree-Based Optical Interconnection Networks  Under Crosstalk Noise Constrain	VLSI
Fault Tolerant Parallel Filters Based on Error Correction Codes	VLSI
Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis	VLSI
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications	VLSI
Functional Constraint  Extraction From Register Transfer Level for  ssATPG	VLSI
Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems	VLSI
High-Frequency Behavioral Multiconductor Cable Modeling for EMI Simulations in Power Electronics	VLSI
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs	VLSI
Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution	VLSI
Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding	VLSI
Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection	VLSI
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes	VLSI
Novel Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm	VLSI
Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms	VLSI
Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count	VLSI
Protein Alignment Systolic Array Throughput Optimization	VLSI
Quaternary Logic Lookup Table in Standard CMOS	VLSI
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing	VLSI
Recursive Approach to the Design of a Parallel Self-Timed Adder	VLSI
Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor	VLSI
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations	VLSI
Robust Relevance Vector Machine With Variational Inference for Improving Virtual Metrology Accuracy	VLSI
Scan Test of Die Logic in 3-D ICs Using TSV Probing	VLSI
Signal Processing With Direct Computations on Compressively Sensed Data	VLSI
Single-Bit Pseudoparallel Processing Low-Oversampling Delta–Sigma Modulator Suitable for SDR Wireless Transmitters	VLSI
Skewed-Load Test Cubes Based on Functional Broadside Tests	VLSI
Task Migrations for Distributed Thermal Management Considering	VLSI
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks	VLSI
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications	VLSI
Time-Based All-Digital Technique for Analog Built-in Self-Test	VLSI
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm	VLSI
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion	VLSI