2014
IEEE VLSI PROJECT TITLES Domain:VLSI
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Language
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Designing a SAR-Based All-Digital Delay-Locked Loop
With Constant Acquisition Cycles Using a Resettable Delay Line
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VLSI
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Runtime Thermal Management for 3-D
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VLSI
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A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus
Prescaler
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VLSI
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Image Quality Assessment for Fake Biometric Detection:
Application to Iris, Fingerprint, and Face Recognition
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VLSI
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A Frame-Level Rate Control Scheme Based on Texture and
Nontexture Rate Models for High Efficiency Video Coding
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VLSI
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A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With
Signal-Independent Delta-I Noise DfT Scheme
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VLSI
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A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS
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VLSI
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A GPU-Accelerated Parallel Shooting Algorithm for
Analysis of Radio Frequency and Microwave Integrated Circuits
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VLSI
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A Low Complexity-High Throughput QC-LDPC Encoder
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VLSI
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A Method for Improving Power Grid Resilience to
Electromigration-Caused via Failures
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VLSI
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A Process-Variation Resilient Current Mode Logic With
Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting,
and DC Gain Using Time-Reference-Based Adaptive Biasing Chain
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VLSI
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A Real-Time Motion-Feature-Extraction VLSI Employing
Digital-Pixel-Sensor-Based Parallel Architecture
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VLSI
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A Synergetic Use of Bloom Filters for Error Detection
and Correction
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VLSI
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A Unified Framework for Outlier Detection in Trace Data
Analysis
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VLSI
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Active power-gating-induced power/ground noise
alleviation using parasitic capacitance of on-chip memories
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VLSI
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An Accuracy-Adjustment Fixed-Width Booth Multiplier
Based on Multilevel Conditional Probability
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VLSI
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Analysis and Characterization of Capacitance Variation
Using Capacitance Measurement Array
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VLSI
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Analysis and Design of a Low-Voltage Low-Power
Double-Tail Comparator
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VLSI
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Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor
Bandpass Filter
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VLSI
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Compensating Modeling Overlay Errors Using the Weighted
Least-Squares Estimation
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VLSI
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Demonstrating HW-SW Transient Error Mitigation on the
Single-Chip Cloud Computer Data Plane
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VLSI
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Design of Self-Timed Reconfigurable Controllers for
Parallel Synchronization via Waggin
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VLSI
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Design Techniques to Improve Blocker Tolerance of
Continuous-Time Δ Σ ADCs
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VLSI
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Effects of Intermittent Faults on the Reliability of a
Reduced Instruction Set Computing (RISC) Microprocessor
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VLSI
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Efficient Hardware Architecture of ηT Pairing
Accelerator Over Characteristic Three
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VLSI
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Energy
Efficiency Optimization Through Codesign of the Transmitter and Receiver in
High-Speed On-Chip Interconnects
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VLSI
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Energy-Efficient Soft-Input Soft-Output Signal Detector
for Iterative MIMO Receivers
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VLSI
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Error
Correction Encoding for Tightly Coupled On-Chip Buses
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VLSI
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Exploiting Same Tag Bits to Improve the Reliability of
the Cache Memories
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VLSI
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Fast and Wide Range Voltage Conversion in Multisupply
Voltage Designs
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VLSI
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Fast Design Optimization Through Simple Kriging
Metamodeling: A Sense Amplifier Case Study
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VLSI
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Fast Radix-10 Multiplication Using Redundant BCD Codes
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VLSI
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Fast Sign Detection Algorithm for the RNS Moduli Set
2n+1-1, 2n-1, 2n
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VLSI
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Fat-Tree-Based Optical Interconnection Networks
Under Crosstalk Noise Constrain
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VLSI
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Fault Tolerant Parallel Filters Based on Error
Correction Codes
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VLSI
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Finite Alphabet Iterative Decoders for LDPC Codes:
Optimization, Architecture and Analysis
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VLSI
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Fully Reused VLSI Architecture of FM0/Manchester
Encoding Using SOLS Technique for DSRC Applications
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VLSI
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Functional Constraint Extraction From Register
Transfer Level for ssATPG
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VLSI
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Hardware Efficient Mixed Radix-25/16/9 FFT for LTE
Systems
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VLSI
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High-Frequency Behavioral Multiconductor Cable Modeling
for EMI Simulations in Power Electronics
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VLSI
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Level-Converting
Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
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VLSI
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Low-Complexity
Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution
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VLSI
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Low-Cost
Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding
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VLSI
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Low-Energy
Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection
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VLSI
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Low-Power
Digital Signal Processor Architecture for Wireless Sensor Nodes
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VLSI
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Novel
Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm
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VLSI
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Parallel
Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms
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VLSI
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Precise
VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low
Adder-Count
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VLSI
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Protein
Alignment Systolic Array Throughput Optimization
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VLSI
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Quaternary Logic Lookup Table in Standard CMOS
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VLSI
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Razor
Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for
Efficient Digital Signal Processing
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VLSI
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Recursive
Approach to the Design of a Parallel Self-Timed Adder
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VLSI
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Reduced-Complexity
Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor
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VLSI
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Reverse
Converter Design via Parallel-Prefix Adders: Novel Components, Methodology,
and Implementations
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VLSI
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Robust
Relevance Vector Machine With Variational Inference for Improving Virtual
Metrology Accuracy
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VLSI
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Scan
Test of Die Logic in 3-D ICs Using TSV Probing
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VLSI
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Signal
Processing With Direct Computations on Compressively Sensed Data
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VLSI
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Single-Bit
Pseudoparallel Processing Low-Oversampling Delta–Sigma Modulator Suitable for
SDR Wireless Transmitters
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VLSI
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Skewed-Load
Test Cubes Based on Functional Broadside Tests
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VLSI
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Task
Migrations for Distributed Thermal Management Considering
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VLSI
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Test
Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks
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VLSI
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The
Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect
Length and Its Circuit Level Implications
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VLSI
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Time-Based
All-Digital Technique for Analog Built-in Self-Test
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VLSI
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Wearout
Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm
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VLSI
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Obstacle-Avoiding
and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion
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VLSI
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Sunday, August 3, 2014
VLSI IEEE 2014 PROJECT TITLES
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